Capacitors have gained wide acceptance and use in today's integrated circuit technology. As is well known, a common capacitor essentially comprises two conductive plates separated by an insulator. It is normal for the conductive plates to be made of aluminum and the insulator to be a dielectric material, such as silicon dioxide (SiO2).
Originally, capacitors were often placed upon a substrate of the integrated circuit (IC) and electrically connected to contact or via structures, as required by design. While these structures were quite effective, their presence caused a topographical aberration in the overlying dielectric material, such that the capacitor's structure would be reflected in the surface of the dielectric layer. As a result, special planarization techniques had to be performed to remove the aberration so that subsequent photolithographic processes were not adversely affected. The effect of the capacitor's aberrations in the photolithographic processes became even more acute as device sizes decreased.
Given the planarization problems associated with the earlier capacitor structures, the semiconductor manufacturing industry sought ways to form the capacitors while lessening their impact on the topography of the overlying dielectric layer. One such approach was to form the capacitor within a contact or via opening. This approach has worked very well for the larger submicron technologies. Because the capacitor was formed within the contact opening or via, its structure did not heavily influence the overlying dielectric layer. As such, the planarization problems present with previous capacitor structures were substantially reduced.
As the design rules have continued to decrease, however, difficulty has arisen with respect to forming a capacitor within these structures. Because smaller device size requires greater precision in the etching processes, the industry is moving toward an etching process known as damascene processing. Because the completed damascene structure has an upper cavity with a width larger than the lower cavity, a stair step topography results within the damascene opening. This damascene process provides more control when forming the trace openings, which in turn allows for manufacturing ICs in the submicron range.
The invention of the damascene process for forming trace openings allowed for the manufacture of ICs in the submicron range. However, because of the damascene's stair step topography, it has proven much more difficult to form capacitors within these damascene openings. One reason for this difficulty, stems from deposition problems that arise due to the deposition of the various layers needed for the capacitor, over the stair step topography. Because of the increased topography, the thickness of the layers that form the capacitor may vary significantly within the damascene structure. This variance in material thickness is difficult to control and makes it very difficult to achieve the desired degree of capacitance. Moreover, because of the number of layers that must be deposited within the smaller portion of the damascene structure, the material necessary to achieve the desired degree of conduction may not be adequately deposited within the damascene structure. Furthermore, voids may also be formed. Because of these uncertainties, the capacitor cannot be easily and consistently manufactured to the desired level.
Accordingly, what is needed in the art is a capacitor structure and a process for forming that capacitor structure that avoids the disadvantages associated with prior art structures and processes.